Embodiments of the invention relate to semiconductor structures, in particular, for semiconductor devices including middle-of-line (MOL) capacitance reduction with integration for self-aligned contact and a method of manufacturing the same.
Nitride stacks are formed by opening contact holes in nitride and oxide layers covering one or more semiconductor devices on a silicon wafer. In a conventional MOL process, the nitride layer is formed to a thickness (e.g., 40 nanometers (nm)) and a thinner oxide layer is formed over the nitride layer (e.g., 10 nm). The oxide and nitride layers are then patterned to open contact holes down to the source/drain regions (also referred to as “active regions”) of the semiconductor devices. In order to reduce the capacitance associated with the post gate (PG) nitride, a thinner nitride layer may be desirable. However, utilizing a thinner nitride layer in a conventional process flow is not feasible because gouging by a chemical mechanical planarization (CMP) process step may cause the semiconductor devices to be susceptible to short circuit failures.